RISC-V is an open standard instruction set architecture (ISA) governed by RISC-V International, freely available for any organization to implement in a processor without licensing fees — the first widely adopted open alternative to the proprietary ISAs that define modern computing.
RISC-V
RISC-V is an open instruction set architecture — the contract between software and silicon, published openly and implementable by anyone without a licence fee. It began at UC Berkeley in 2010 and is now governed by RISC-V International, a Swiss-domiciled non-profit with a large member coalition including chip companies, hyperscalers and universities.
- The ISA is the contract - Base integer sets plus modular standard extensions, so an implementer takes what the product needs rather than a monolith.
- Openly licensed - No per-unit royalty and no architectural licence, which is the whole reason it exists.
- Ratified specifications - Extensions move through a formal ratification process rather than being announced.
- Broad coalition - Members span AI accelerator startups, established semiconductor vendors, and national programs pursuing supply-chain independence.
RISC-V matters to API research for a reason that is easy to miss. It proves that the semiconductor industry can build, govern and adopt an open standard with a neutral host and a real ratification process — it is simply that the standard describes parts rather than interfaces. An open ISA tells a compiler how to emit instructions; it tells an agent nothing about whether a part is in production, what its errata are, or when it goes end-of-life. The State of Compute & Hardware APIs scores RISC-V International itself at 34.9, and the silicon layer it helps govern at 10.7. The capability for standards work is clearly present. It has not yet been pointed at the network.
