Compute Express Link is an open interconnect standard built on the PCI Express physical layer that adds cache coherency and memory semantics, allowing accelerators, memory expanders and pooled memory to be shared coherently between a host processor and attached devices.
CXL
CXL (Compute Express Link) takes the PCIe physical layer and adds what PCIe lacks: cache coherency and memory semantics. A CXL-attached device can share memory coherently with the host rather than shuttling buffers across a bus, which is the enabling piece for memory expansion, memory pooling across a rack, and accelerators that behave like part of the machine.
- Three protocols - CXL.io for discovery and configuration, CXL.cache for device access to host memory, CXL.mem for host access to device memory.
- Memory pooling and sharing - Later revisions allow memory to be disaggregated and allocated across hosts, which is a data-center economics story as much as a technical one.
- Consolidated the field - Competing coherent-interconnect efforts folded into the CXL Consortium, leaving one standard rather than several.
- Built on PCIe - It reuses the electrical and link layers, which is why adoption tracks PCIe generations.
CXL is a good example of the semiconductor industry doing standards work well — an open consortium, genuine competitor consolidation, and a specification that solves a real architectural problem. The State of Compute & Hardware APIs groups it with PCIe, UCIe and JEDEC to make its central point about this market: the stack is standardized to a degree few industries approach, and every one of those standards describes how parts talk to parts. The report scores the layer that publishes them at 10.7, because none of that standardization ever reaches a network client.
Referenced in API Evangelist papers
This standard shows up in my published research. These reports read the machine-readable evidence provider by provider — and put this standard in the context of a real sector.
The State of Compute & Hardware APIs
Named in the report's standards layer alongside PCIe, UCIe and JEDEC — the group of specifications that govern how parts talk to parts, and never how a client talks to the product.
